Semicon 2.0 to target 7nm-3nm chip technologies and train 100,000 design engineers, says IT minister

According to the minister of Electronics and IT, railways, and information and broadcasting, India will aim to develop advanced semiconductor process technologies in the 7-nanometre to 3-nanometre range over the next eight years under the next phase of its semiconductor programme, Semicon 2.0.

The programme will broaden the government’s focus beyond semiconductor fabrication and packaging to seven areas: chip design, manufacturing equipment, materials, fabs, advanced packaging, research and talent development.

Semicon 2.0 will also target the training of 100,000 semiconductor design engineers, with the longer-term objective of positioning India as a global hub for chip design.

In chip design, the government will focus on six areas: compute, memory, radio frequency, power, networking and sensors. The programme will also provide incentives for domestic semiconductor equipment manufacturing and production of specialised materials, including chemicals and gases required for chip manufacturing.

India currently has two semiconductor fabs under development and plans to support additional fabrication facilities. Support for semiconductor packaging will continue, with greater emphasis on advanced packaging technologies.

The minister said 12 semiconductor units involving cumulative investments of around $20 billion have been approved over the past five years under the first phase of the Semicon India programme.

Three facilities have now begun commercial production. Micron commenced production on February 28, 2026, followed by Kaynes on March 31 and CG Power on July 4.

The government launched the Semicon India programme in 2021 with an initial outlay of around $10 billion to support semiconductor fabrication and packaging.

He said the strategy has focused on developing a broader semiconductor ecosystem rather than pursuing individual projects without supporting capabilities. Global companies have also invested more than $3 billion in India outside the Semicon India programme, he added.

Chip design will remain a major focus under Semicon 2.0. Through the Chips to Startup programme, electronic design automation (EDA) tools have been provided to more than 320 universities and startups.

The government had initially targeted creating a pool of 85,000 skilled semiconductor engineers over 10 years. Semicon 2.0 will now raise this ambition to 100,000 design engineers.

The minister said Indian engineers are already involved in designing advanced chips at 2nm and 3nm process nodes for global semiconductor companies operating in India.

Under the Design Linked Incentive (DLI) scheme, 105 startups have been supported, with 24 receiving financial assistance totalling $83 million. Fifteen of these startups have subsequently raised $118.5 million in venture capital funding.

India’s semiconductor push is being supported by the expansion of its electronics manufacturing ecosystem. He said electronics manufacturing in the country has crossed $130 billion, while electronics exports have exceeded $48 billion.