Zepto Logic Technologies has entered into a Rs 2.5 billion memorandum of understanding (MoU) with the government of Tamil Nadu to build a semiconductor fabless design facility and a skilling centre for very large-scale integration (VLSI) and embedded systems talent development.
The fabless design unit will focus on system-on-chips (SoCs), intellectual property (IP), application-specific integrated circuits (ASICs), and field programmable gate arrays (FPGAs).
According to Zepto Logic, its core design activities will be supported by its associate firm, Caliber Embedded Technologies, Coimbatore. The startup noted that it also aims to gradually foster an ecosystem for domestic chip design, intellectual property (IP) creation, semiconductor research and development, and downstream manufacturing.
Further, the proposal additionally includes setting up a long-term semiconductor innovation and training campus. Zepto Logic said it has previously contributed to India’s indigenous processor ecosystem through IP aligned with Centre for Development of Advanced Computing’s (CDAC) Vega and Indian Institute of Technology (IIT)-Madras’ Shakti RISC-V programmes.